1. Field of the Invention
The invention relates in general to a multimedia receiving interface, and more particularly to a circuit architecture of a multimedia receiving interface.
2. Description of the Related Art
With the constant progress of electronic technologies, display apparatuses of all diversities are becoming more and more popular. Various kinds of electronic device, such as television systems, computer systems, projectors, digital cameras, disk players, mobile phones and game consoles, all need a good video/audio transmission interface. To optimize the compatibility with other peripheral devices, many electronic devices simultaneously includes several multimedia receiving interfaces such as High-Definition Multimedia Interface (HDMI), Mobile High-Definition Link (MHL) and DisplayPort (DP) standards.
FIG. 1 shows a function block of a front-end of an HMDI receiving circuit. As shown in FIG. 1, four pairs of differential signals CK, B, G and R are inputted into the HDMI receiver. The clock signal CK is provided to a clock signal receiver 101 and a phase-locked loop (PLL) 102, and the image data signals B, G and R are respectively provided to analog front-end circuits 110A to 110C. The PLL 102 generates a ten-fold frequency signal or a forty-fold frequency signal from the clock signal (i.e., a clock frequency of a transmitter), and transmits the generated signal to the phase adjusting circuits 140A to 140C. Sampling circuits 120A to 120C sample input signals by the sampling clock signals provided by the phase adjusting circuits 140A to 140C. Through multiplexers 150A to 150C, sample results of the sampling circuits 120A to 120C are respectively transmitted to digital clock data recovery (DCDR) circuits 130A to 130C. Detection results of the DCDR circuits 130A to 130C are feedback to corresponding phase adjusting circuits 140A to 140C, which then accordingly adjust phases of respective output signals (i.e., sampling clock signals utilized by the sampling circuits 120A to 120C), so that the sampling circuits 120A to 120C may generate preferred sample results.
FIG. 2 shows a function block of a front-end of an MHL receiving circuit. A pair of differential input signals can carry a clock signal and a data signal, and are provided to a clock signal receiver 201 and an analog front-end circuit 210. A clock signal extracted from the clock signal receiver 201 and a data signal having been preliminarily processed by the analog front-end circuit 210 are provided to an analog clock data recovery (ACDR) circuit 220 for the use of clock recovery. An output signal from the ACDR circuit 220 is transmitted to a subsequent circuit through a demultiplexer 250.
FIG. 3 shows a function block of a front-end of a DP receiving circuit. As shown in FIG. 3, four pairs of differential image data signals Data#0, Data#1, Data#2 and Data#3 are inputted into a DP receiver, and are respectively provided to analog front-end circuits 310A to 310D. Signals having been preliminarily processed by the analog front-end circuits 310A to 310D are respectively provided to subsequent ACDR circuits 320A to 320D for clock data recovery.
In the prior art, an electronic device simultaneously provided with an HDMI receiving circuit, an MHL receiving circuit and a DP receiving circuit is designed to include three independent receiving circuits, hence high hardware costs.